1. Field of the Invention
The present invention generally relates to a RFID device having a nonvolatile ferroelectric memory, and more specifically, to a technology of supplying a high voltage only to a memory cell array area of a FeRAM in the RFID device and a low voltage to peripheral areas to reduce power consumption.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and preserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the high residual polarization characteristic of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FeRAM are disclosed in U.S. Pat. No. 6,775,172 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.
FIG. 1 is a diagram illustrating a Radio Frequency Identification (hereinafter, referred to as “RFID”) device including a FeRAM.
The RFID includes an antenna 10, an analog block 20, a digital block 30 and a memory 40.
The antenna 10 transmits and receives a radio frequency signal of an external reader or writer.
The analog block 20 includes a voltage multiplier 21, a voltage limiter 22, a modulator 23, a demodulator 24, a voltage doubler 25, a power-on reset unit 26 and a clock generating unit 27.
The voltage multiplier 21 generates a power voltage VDD of the RFID device in response to the radio frequency signal applied from the antenna 10.
The voltage limiter 22 limits a voltage of the radio frequency signal applied from the antenna 10.
The modulator 23 modulates a response signal Response applied from the digital block 20 to transmit the signal Response to the antenna 10.
The demodulator 24 detects an operation command signal from the radio frequency signal applied from the antenna 10 by a power voltage VDD to output the command signal CMD to the digital block 30.
The voltage doubler 25 boosts the power voltage VCC applied from the voltage multiplier 21 to supply a boosting voltage VDD2 having a swing width twice as large as the power voltage VDD to the memory 40.
The power-on reset unit 26 senses the power voltage VDD applied from the voltage multiplier 21 to output a power-on reset signal POR for controlling a reset operation to the digital block 30.
The clock generating unit 27 generates a clock signal CLK by the power voltage VDD.
The digital block 30 receives the power voltage VDD, the power-on reset signal POR, the clock signal CLK and the command signal CMD from the analog block 20 to output the response signal Response to the analog block 20. The digital block 30 outputs an address ADD, data I/O, a control signal CTR and the clock signal CLK to the memory 40.
The memory 40 has a plurality of memory cells each including a nonvolatile ferroelectric capacitor.
FIG. 2 is a waveform diagram illustrating the relationship between power consumption and the output voltage of the voltage multiplier of the RFID device of FIG. 1.
In the RFID device, the output voltage VDD of the voltage multiplier 21 of FIG. 1 which is a voltage generator becomes higher when the amount of operating current is small as shown in graph A, and the output voltage VDD becomes lower when the amount of current become large as shown in graph B.
In the RFID device, the analog block 20 and the digital block 30 can be driven only by the low voltage VDD while the memory 40 requires the high voltage VDD2. As a result, the memory 40 receives the high voltage VDD2 from the voltage doubler 25.
The memory 40 has a memory cell array area (not shown) and a peripheral area. The high voltage VDD2 supplied from the voltage doubler 25 of FIG. 1 is required from the memory cell array area (not shown), and the peripheral area can be driven by a voltage lower than the voltage VDD2.
Other areas can be driven only by a low voltage although a high voltage is required in the memory cell array area (not shown) of the memory 40. However, a high voltage is supplied to all areas of the memory 40, which results in unnecessary power consumption.